1-3 years of experience required:
Engineers who can design, architect, and implement:
- VoIP Architecture and can write drivers for Analog Telephony, ISDN and RoIP. Implementation of Networking Stack and Protocols.
- Waveforms and DSP algorithms using VHDL or Verilog targeting Software Defined Radio (SDR) hardware.
Responsibilities:
- Develop DSP algorithms, and conduct performance simulations.
- Perform FPGA/embedded software/hardware system integration testing, verification and debugging.
Key Skills and Characteristics:
- FPGA Design experience, preferably Xilinx design flow, BlackFin, Freescale.
- Design experience using MATLAB, Simulink, Xilinx System Generator, Vivado IDE & TCL toolchains.
- Design experience in wireless communication digital front ends (interpolators, decimators, DSP Filters, DUC, DDC).
- Familiarity with Xilinx Zynq architecture ,VOIP Architecture and Embedded Linux Architecture.
- Experience in RF DSP algorithm design and implementation in FPGA fabric.
- Experience with Xilinx and Intel/Altera FPGAs.
- Knowledge of signal processing algorithms, modulations and hardware design.
- Perform FPGA/embedded software/hardware system integration testing, verification and debugging.
- Hands-on experience with hardware prototype boards, performance evaluation and system debugging.
- Hands-on experience in using test equipment (Oscilloscopes, Spectrum Analyzers, Vector Signal Generators, and similar).
- Strong Grip on C\ C++.
- Understanding of Python Language.
- Understanding of SoC architecture.
- Understanding of VoIP.
- Understanding of Networking Stack.
- Good analytical, problem solving and debugging skills.
- Strong communications skills, oral and written (English).
Qualifications:
Bachelor’s or Master’s Degree in Electronics\ Electrical \ Computer\ Software Engineering with Final Year project in mentioned requirements or 3+ years’ experience in relevance.
Resumes must be directly sent to designated emails. (Please don’t forward resumes to any other email address.) [email protected] [email protected] [email protected] [email protected]